1. Field of Invention
The present invention relates to a preparation method of a semiconductor device substrate, specifically, to a preparation method of a full-isolated silicon on insulator (SOI) substrate with hybrid crystal orientations, which belongs to the field of semiconductor device fabrication.
2. Description of Related Arts
A complementary metal oxide semiconductor (CMOS) device is a semiconductor device integrating an N-channel metal oxide semiconductor (NMOS) diode and a P-channel metal oxide semiconductor (PMOS) diode on the same substrate. With the development of the CMOS technology, how to control the stability of the device and improve the performance of the device has become an serious challenge encountered by gradually reduced device size. SOI (silicon on Insulator) refers to the silicon on insulator technology, the SOI technology reduces source-drain parasitic capacitance, so the speed of an SOI circuit is significantly improved as compared with the speed of a conventional bulk-silicon circuit, and at the same time, the SOI has a series of advantages such as small short-channel effect, desired latch-up prevention, and simple process, so the SOI technology has gradually become a main technology for fabricating a very large scale silicon integrated circuit (IC) with high-speed, low-power consumption, high-integration, and high-reliability. The SOI is generally constructed by the following three layers: a thin monocrystalline silicon top layer, on which an IC is formed; a very-thin buried oxide (BOX), that is, an silicon dioxide insulating intermediate layer; and a very-thick bulk substrate silicon substrate layer, which mainly provide mechanical support for the above two layers. An oxide layer in the SOI structure isolates the silicon film layer above from the bulk silicon substrate layer, so a large area of a p-n junction is replaced with a dielectric isolation. A source region and a drain region extend downwards to the BOX, which effectively reduces the leakage current and junction capacitance.
In addition, for a Si material, hole mobility in a (110) Si substrate is increased by more than twice as compared with that in a convention (100) Si substrate; and electron mobility is the highest in the (100) Si substrate. In a current CMOS IC, the NMOS and the PMOS are both fabricated on the (100) silicon substrate. Since the (100) Si substrate has the highest electron mobility, which is higher than the hole mobility by about 2-4 times, it is required to design a PMOS with larger gate width to balance the NMOS, and therefore, it is hard to obtain a CMOS device and circuit with higher performance In order to fully utilize the advantage that the carrier mobility depends on Si surface orientation, Yang et al. in the IBM Company developed a new technology of fabricating a CMOS circuit by adopting a Si substrate with hybrid crystal orientations. Yang M, leong M, Shi L et al. have introduced their technology in the paper entitled “High performance CMOS fabricated on hybrid substrate with different crystal orientations” in “Digest of Technical Paper of International Electron Devices Meeting” in 2003. Through bonding and selective epitaxial growth, an NMOS device is fabricated on a (100) Si surface with a BOX, and a PMOS device is fabricated on a (110) Si surface, so that the performance of the PMOS device can be greatly improved. When Ioff=100 nA/μm, the drive current of the PMOS device on the (110) substrate is increased by 45%. The disadvantage thereof is that the PMOS device fabricated on the epitaxial layer has no BOX to isolate the PMOS device with the substrate, and therefore the device performance is still affected. The patent document of US patent No. US2007/0281446A1 discloses a fabrication method of an SOI substrate with hybrid crystal orientations, in which a bottom silicon is exposed by etching a trench, and a (110) silicon material with a crystal orientation different from that of an original (100) top silicon is epitaxially grown from the bottom silicon by the lateral selective epitaxial growth process, thereby obtaining an SOI substrate with hybrid crystal orientations. The method has a complicated fabrication process, and the (110) silicon material thereof is obtained by direct epitaxial growth of the bottom silicon. However, along with the further reduction of characteristics dimension of the device, the low hole mobility of the common silicon material will become one of the bottlenecks for improving of the device performance.
In order to further improve the performance of the CMOS IC, the present invention provides a new technology for a full-isolated SOI substrate with hybrid crystal orientations, which provides a strained silicon material while implementing the SOI substrate with hybrid crystal orientations, and can provide a substrate having higher mobility respectively for the NMOS and the PMOS.